gridrf/solutions · reference design
SDR Receiver Solutions with AD9361 and ZYNQ
A complete data path from antenna to Ethernet, combining a 70 MHz–6 GHz RF agile transceiver with the Zynq-7000 SoC. HDL, Linux drivers, and host SDKs help you build custom receivers faster.
Signal Chain
RF Front End
AD9361 2R2T, 70 MHz–6 GHz, 56 MHz instantaneous bandwidth, 12-bit ADC/DAC, integrated AGC and quadrature calibration.
PL Digital Processing
DDC/DUC chains, CIC/FIR decimation, FFT spectrum processing, and custom demodulation IP in ZYNQ programmable logic.
PS System Control
Dual-core ARM A9 with PetaLinux, high-throughput AXI-DMA, web configuration, and remote upgrades.
Host Interface
Gigabit Ethernet and USB 3.0, libiio compatibility, and C, Python, MATLAB, and GNU Radio interfaces.
Deliverables
Hardware
- AD9361 + ZYNQ-7020 schematic and PCB reference design
- RF front-end matching and calibration guidance
- Clock tree design with 10 MHz reference or GPSDO
- Thermal, mechanical, and EMC support
FPGA & Embedded
- Open-source HDL reference project (Vivado 2023.2)
- DDC/DUC, FFT, and demodulation IP source code
- PetaLinux system image and device tree
- Complete AXI register map documentation
Software
- libgridrf host library for Windows and Linux
- Python and MATLAB acquisition examples
- GNU Radio source blocks
- Production test and calibration software
Applications
Spectrum Monitoring
- Wideband sweeping and occupancy statistics
- Signal recording, playback, and offline analysis
- Interference and unauthorized transmitter investigation
Communications & Navigation
- GNSS IF capture and anti-jamming research
- Protocol analysis and teaching labs
- UAV link detection and positioning
Custom Receivers
- Coherent multi-channel receiver expansion
- Custom demodulation algorithm integration
- Support from prototype to production
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